1. Field of the Invention
The present invention relates to a test mode setup, and more particularly, to a semiconductor device for a test mode setup which allows a synchronous DRAM (SDRAM) user to prevent an unwanted test mode from being set up.
2. Discussion of the Related Art
A conventional semiconductor device for a test mode setup will be described with reference to the accompanying drawings.
FIG. 1 is a block diagram illustrating a conventional semiconductor device for a test mode setup. FIG. 2 is a timing chart illustrating a setup operation of a conventional semiconductor device for a test mode setup.
As shown in FIG. 1, the conventional semiconductor device for a test mode setup includes a command decoder 1, a test register 2, and a test decoder 3. The command decoder 1 decodes external input signals, i.e., a clock (CLK) signal, a row address strobe bar (RASB) signal, a column address strobe bar (CASB) signal, a chip select bar (CSB) signal, a write enable bar (WEB) signal, and a seventh address (A&lt;7&gt;) signal. The test register 2 stores a logic value of test decoding address TDA&lt;i:j&gt; signal of K-bit in response to a test register setup (TRS) signal decoded from the command decoder 1, and outputs a TDG&lt;i:j&gt; signal to the test decoder 3. The test decoder 3 outputs a test mode signal corresponding to the output TDG&lt;i:j&gt; of the test register 2.
The setup operation of the conventional semiconductor device for a test mode setup will be described below.
As shown in FIG. 2, the test mode is set up when the CLK signal repeats low and high in turn, a clock enable (CKE) signal is high in n-1 clock period, the A&lt;7&gt; signal is high in n clock period, the CSB signal, the RASB signal, the CASB signal and the WEB signal are low in n clock period, and the TDA&lt;i:j&gt; has a given logic value. In other words, the test mode setup is performed in such a manner that a test mode is operated if a logic value of the A&lt;7&gt; signal input during setting the test register is "1", while a normal mode is operated if the logic value is "0".
As shown in FIGS. 1 and 2, the command decoder 1 outputs the TRS signal of high level to the test register 2 when the inputs CLK, RASB, CASB, CSB, WEB, and A&lt;7&gt; of the command decoder 1 have the logic values as described above. When the TRS signal is high, the logic value of the TDA&lt;i:j&gt; signal of K bit is stored in the test register 2. There is the probability of 1/2.sup.5 that the command decoder 1 outputs the TRS signal of high level.
As aforementioned, the logic value of the TDA&lt;i:j&gt; signal is stored in the test register 2 when the TRS signal is high. The TRS signal is maintained at high pulse for a certain time period and then becomes low. When the TRS signal is low, the logic value previously stored in the test register 2 is maintained as it is even though the logic value of the TDA&lt;i:j&gt; signal is varied.
After the logic value of the TDA&lt;i:j&gt; signal is stored in the test register 2, the test register 2 outputs the TDG&lt;i:j&gt; signal to the test decoder 3. The test decoder 3 outputs the test mode signal corresponding to the logic value input thereto. At this time, the test mode signal is high.
The conventional semiconductor device for a test mode setup has a problem that an unwanted test mode setup may occur because the command decoder has the same logic values as those of a mode register set (MRS) which is one of combinations of synchronous DRAM commands, except for the logic value of the A&lt;7&gt;.